| Job Description:
The successful candidate will work with senior members to be...Job Description:
The successful candidate will work with senior members to become familiar with SOC/FPGA product line and provide application designs, solutions and design services for customers. The candidate will be responsible for developing RTL designs targeted for FPGA family of devices. Successful candidates will be able to gather requirements, put together design documents, code in RTL to good coding standards, put together functional simulation and validation plans, run functional simulations and validate designs or customer hardware.
Qualifications:
- Requires a Bachelors or Masters Degree in Electrical/Electronics Engineering with a minimum of 8 years experience
Required Skills:
- Clear understanding of logic design concepts
- Solid Verilog/VHDL programming skills
- Ability to write test benches for functional simulation at both system level and block level
- Good understanding and exposure to developing low power designs and closing timing
- Working knowledge of communication protocols and bus architectures such as PCIe, SATA, XAUI, SGMII, Fiber Channel, CPRI, 10G-KR etc.
- Desired to have knowledge of DSP concepts
- Experience in C/C++ is a plus
- Ability to review board level schematics and understanding of basic circuits
- Ability to work with various lab equipment such as oscilloscopes, logic analyzers, bus analyzers etc
- Ability to multi-task
- Ability to be part of a dynamic, team oriented applications engineering organization
- Comfortable with a reporting structure in Shenzhen, India and the United States.
- Willing to participate and interact with a Supervisor and colleagues in India and the United States which will involve communication during “non-standard” working hours.
- Excellent communication skills and fluent Mandarin speaking and English Language, written and spoken.
